Shunyaya Symbolic Mathematical Hardware – Silicon: Targets, Datapath & Pipeline (7.1–7.3)

7.1 — Targets and philosophy
Targets. MCU-class DSP blocks, FPGA soft-IP, and ASIC tiles.
Philosophy. Same math, same knobs, same answers. Always clamp: a := clamp(a, -1+eps_a, +1-eps_a). Map to rapidity u := atanh(a), compose in u, invert a := tanh(u), then re-clamp. Collapse parity holds: phi((m,a)) = m.
Deliverables. Minimal SSM-ALU (lane ops), streaming SSACC accumulator {U,W}, and a tiny ISA to drive them.
Determinism. Knobs (eps_a, eps_w, gamma, division_policy, LUT IDs, rounding mode) and word-lengths live in the manifest; changing any invalidates bit-identical claims.

7.2 — Block diagram (two-lane datapath)
Buses (lockstep).
M-BUS (value lane). IEEE-754 magnitudes; legacy arithmetic unchanged.
A-BUS (confidence lane). Bounded alignment a in (-1,+1).
U-BUS (internal fast lane). u := atanh(a) for 1-cycle add/sub/scale.

Blocks.

  1. SSM-ALUa -> clamp, u := atanh(a), compose in u, a' := tanh(u) and re-clamp.
  2. SSACC — registers {U,W}, guarded divide, flush to a_out.
  3. Quality DMA (optional) — side-channel movers for A/U-BUS.
  4. Knob MMIO — memory-mapped parameters + read-only manifest.

ASCII sketch (two short rows to avoid wrap).
Value lane (unchanged):
[M-BUS:m] -> [legacy ALU] -> ...
Alignment lane + SSACC (streaming fuse):
[A-BUS:a] -> [Clamp/Map a->u] -> [Compose u]
[SSACC {U,W}] -(streaming fuse)-> [Inv/Clamp u->a] -> [A-BUS:a']

Note (streaming fuse equations). U += w*atanh(a), W += w, a_out := tanh(U/max(W, eps_w)).

7.3 — SSM-ALU pipeline (3 stages, normative)
Stage 1 — Clamp/Map. a := clamp(a, -1+eps_a, +1-eps_a) ; u := atanh(a).
Stage 2 — Compose. u := u1 ± u2, or u := r*u, or streaming write U := U + w*u, W := W + w.
Stage 3 — Inverse/Bound. a := tanh(u) or a := tanh(U / max(W, eps_w)) ; then re-clamp to (-1+eps_a,+1-eps_a).
Properties. Single-issue; no NaN/Inf paths; parity with the software reference for identical knobs, word-lengths, and rounding.


Navigation
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Directory of Pages
SSMH – Table of Contents


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https://github.com/OMPSHUNYAYA/Symbolic-Mathematical-Hardware


Disclaimer
The contents in the Shunyaya Symbolic Mathematical Hardware (SSMH) materials are research/observation material. They are not engineering advice, not a safety standard or certification, and not operational guidance. Do not use for safety-critical, medical, legal, or financial decisions. Use at your own discretion; no warranties are provided; results depend on correct implementation and inputs.