Shunyaya Symbolic Mathematical Hardware – Silicon, ISA & Timing (2.4–2.7)

2.4 — Silicon blocks (small, composable IP)

  • SSM-ALU (lane ops). Three stages: clamp/map (u := atanh(a_c)), compose (u' = u_f ⊕ u_g via +, -, scale), inverse/re-clamp (a' := tanh(u')). tanh/atanh via LUT+poly sized to keep |error_a| <= 1e-6.
  • SSACC tile (streaming). Registers {U,W}, guarded divide, publish a_out := tanh( U / max(W, eps_w) ). One input per cycle; flush emits the fused lane.
  • Quality DMA (optional). Side-channel for A/U-BUS so legacy math can ignore a while SSM units consume it.
  • Determinism. Publish rounding occurs only at I/O boundaries; collapse always holds: phi((m,a)) = m.

2.5 — ISA-like ops (scalar first, then SIMD)

  • Mapping. SATANH: a -> u ; STANH: u -> a
  • Compose. SUADD: u1,u2 -> u ; SUSUB: u1,u2 -> u ; SUSCALE: u,r -> u
  • Arithmetic (symmetric lane).
    SMUL_SYM: (m1,a1),(m2,a2) -> (m1*m2, a_out) with a_out = (a1 + a2) / (1 + a1*a2)
    SDIV_SYM: (m_f,a_f),(m_g,a_g) -> (m_f/m_g, a_out) with a_out = (a_f - a_g) / (1 - a_f*a_g) (magnitude follows division_policy)
  • Streaming. SSUM_UW: a,w ⇒ {U += w*atanh(clamp(a)); W += w} ; SFLUSH_UW ⇒ a_out = tanh(U / max(W, eps_w))
  • Utility. SCOLLAPSE: (m,a) -> m ; SSCALE: (m,a),k -> (k*m, sign(k)*a) (then clamp)
  • SIMD. Vector forms of all ops plus fused-accumulate variants for dot/fold patterns.

2.6 — Memory map (knobs and manifests)

  • Numerical knobs. eps_a (e.g., 1e-6), eps_w (e.g., 1e-12), denom_soft_min, gamma.
  • Policies. division_policy in {"strict","soft","meadow"}, gate_enable, gate gain g_t.
  • Bands. Threshold table for A++/A+/A0/A-/A-- (overrides must be declared).
  • Tables. LUT IDs for tanh/atanh with max-error bounds.
  • Manifest (ASCII). Records knob values, build ID, and a conformance vector checksum.
  • Determinism rule. Changing any knob or LUT invalidates bit-identical replay claims; emit a new manifest.

2.7 — Timing, latency, throughput (design targets)

  • u-space ops. u_add/u_sub/u_scale in ~1 cycle at MCU/FPGA DSP-class clocks.
  • Nonlinear maps. tanh/atanh latency set by LUT depth/poly degree (typ. 1–3 cycles).
  • SSACC. Per-sample accumulate in 1 cycle; SFLUSH_UW dominated by divider + tanh.
  • Pipeline sketch. L_total ≈ L_map + L_compose + L_inverse ; sustained streaming rate = 1 sample / cycle once pipeline is full.

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