7.10 — Reset, exceptions, and clamp discipline
• Clamp everywhere. Before any atanh and after any tanh: a := clamp(a, -1+eps_a, +1-eps_a).
• No NaN/Inf. atanh(clamp(a)) is finite; soft-divide remains in the magnitude policy only, never in the lane.
• Reset semantics. SSACC reset clears {U,W}; SSM-ALU retains knob registers (manifested).
• Telemetry on fault. If any guard trips, emit (m,a) with band A-- and increment a counter; never hide m.
7.11 — Silicon bring-up plan (lab recipe)
• Vectors. Feed E1–E9 (verification pack) from ROM; compare on-chip outputs vs golden within tolerance.
• Batch = stream. Permute inputs through SSACC; confirm lane equality within budget (batch == stream == shuffled).
• Clamp edge. Inject a ≈ ±(1 - 1e-6); verify finite u, bounded a.
• Throughput. Saturate SUADD/SUSUB; check 1-cycle cadence without bubbles.
• Power. Toggle GATE_ENABLE and SSACC activity to measure dynamic headroom.
• Extended. Run E10 (fixed-point parity), E11 (shuffle invariance), E12 (near-zero division policy) and archive the conformance_checksum.
7.12 — Integration patterns (drop-in)
• Side-car mode. Carry a alongside m; legacy compute reads m only.
• Opt-in compute. Route selected kernels via SSM-ALU/SSACC; others pass through unchanged.
• Telemetry taps. Mirror (m,a) and bands to observability without perturbing graphs.
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SSMH – Table of Contents
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