Shunyaya Symbolic Mathematical Hardware – Ports & Silicon Mapping (1.6–1.7)

1.6 — Connectors (ports) that match real operations

  • Arithmetic ports. s_sum, s_add, s_sub, s_mul, s_div, s_pow, s_unary.
  • Decision ports.s_gt, s_eq emit numeric scores/bands without altering m.
    • Example (one option): s_gt(x,y) = tanh( beta_m*(m_x - m_y) + beta_a*(a_x - a_y) ).
  • Alignment-only gate. a_env := clamp( g_t * a_op, -1+eps_a, +1-eps_a ) with m untouched; g_t in [0,1].
  • Policy note. Always clamp before any atanh and re-clamp before publish; collapse remains phi((m,a)) = m.

1.7 — Kernel-to-silicon mapping (small by design)

  • SSM-ALU (lane ops). Three stages: clamp/map (u := atanh(a_c)), compose in u (+, -, scale), inverse/re-clamp (a := tanh(u')).
  • SSACC tile (streaming). Minimal accumulator with registers {U,W} and guarded divide for U/W; publish a_out := tanh( U / max(W, eps_w) ).
  • Buses. Magnitude lane M-BUS and confidence lane A-BUS/U-BUS in lockstep; publish rounding only at I/O for determinism.
  • Fixed-point profiles (typical). a in Q1.15 or Q2.14; u in Q2.30 or Q5.27; LUT max error <= 1e-6 in a.
  • Parity targets. Software vs RTL numeric parity within declared tolerances; identical knobs ⇒ identical replays.

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