Shunyaya Symbolic Mathematical Hardware – Ports, Buses & Kernel Pipeline (2.1–2.3)

2.1 — Connector layer (ports and semantics)
Principle. Every public port consumes and emits pairs x := (m,a) and preserves collapse parity phi((m,a)) = m. Clamp the lane before any combine, and re-clamp on output. Determinism: fixed knobs ⇒ identical outputs.

  • s_sum({(m_i,a_i)}, {w_i}) -> (m_out, a_out)
    m_out := sum_i m_i
    U := sum_i w_i*atanh(clamp(a_i)) ; W := sum_i w_i ; a_out := tanh( U / max(W, eps_w) )
    Defaults: if {w_i} not supplied, use w_i := |m_i|^gamma (default gamma = 1).
    Property: order-invariant (batch == stream == shuffled, within epsilon).
  • s_add((m1,a1),(m2,a2))
    m_out := m1 + m2
    a_out := tanh( ( w1*atanh(clamp(a1)) + w2*atanh(clamp(a2)) ) / max(w1+w2, eps_w) )
    with w1 := |m1|^gamma, w2 := |m2|^gamma.
  • s_sub((m1,a1),(m2,a2))
    m_out := m1 - m2
    a_out := tanh( ( w1*atanh(clamp(a1)) + w2*atanh(clamp(-a2)) ) / max(w1+w2, eps_w) )
    (Note: subtraction is addition by k = -1, so the second lane flips sign; weights stay |m|^gamma.)
  • s_mul((m1,a1),(m2,a2))
    m_out := m1*m2
    a_out := tanh( atanh(clamp(a1)) + atanh(clamp(a2)) )
    Closed form: a_out = (a1 + a2) / (1 + a1*a2) (after clamping).
  • s_div((m_f,a_f),(m_g,a_g))
    m_out := m_f / m_g under chosen magnitude policy (strict | meadow | soft)
    a_out := tanh( atanh(clamp(a_f)) - atanh(clamp(a_g)) )
    Closed form: a_out = (a_f - a_g) / (1 - a_f*a_g) (after clamping).
  • s_pow((m,a), r)
    m_out := m^r (domain rule below)
    a_out := tanh( r*atanh(clamp(a)) )
    Domain rule (real outputs): if m > 0, any real r; if m = 0, require r > 0; if m < 0, require integer r (sign per parity) or reject/emit declared sentinel for the lane while keeping m per policy.
  • s_unary_f((m,a)) for monotone f
    m_out := f(m) ; S_f(m) := m*f'(m)/f(m) (dimensionless log-slope)
    a_out := tanh( S_f(m) * atanh(clamp(a)) )
    (Require f monotone on the operating range and f(m) != 0; S_f may be negative, flipping the lane.)
  • Decision ports s_gt((x1),(x2)), s_eq((x1),(x2))
    Emit bounded numeric scores/bands from (m,a); do not modify m.
    Example scores (one option):
    s_gt(x1,x2) := tanh( beta_m*(m1 - m2) + beta_a*(a1 - a2) )
    s_eq(x1,x2) := 1 - 2*tanh( beta_m*|m1 - m2| + beta_a*|a1 - a2| )
  • Alignment-only gate PORT_gate(a_op, g_t in [0,1]) -> a_env
    a_env := clamp( g_t * a_op, -1+eps_a, +1-eps_a ) ; magnitude is untouched.
    (Use to apply environment/policy scaling to the lane.)

2.2 — Bus model (two lanes in lockstep)

  • M-BUS (magnitude). Classical IEEE-754 magnitudes; legacy arithmetic and pipeline policies apply.
  • A-BUS (alignment). Carries bounded a in (-1,+1).
  • U-BUS (optional). Carries rapidities u := atanh(a) for low-latency add/sub/scale.
  • Lockstep guarantee. For every op, M-BUS and A/U-BUS advance together; collapse parity holds at any boundary (phi((m,a)) = m).

2.3 — Kernel (three-stage micro-ops, normative)

  • Stage 1 — Clamp/Map. a := clamp(a, -1+eps_a, +1-eps_a) ; u := atanh(a)
  • Stage 2 — Compose. u := u_add / u_sub or u := r*u (scalar scale) or streaming U := U + w*u, W := W + w
  • Stage 3 — Inverse/Bound. a := tanh(u) or a := tanh( U / max(W, eps_w) ) ; re-clamp to (-1+eps_a, +1-eps_a)

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The contents in the Shunyaya Symbolic Mathematical Hardware (SSMH) materials are research/observation material. They are not engineering advice, not a safety standard or certification, and not operational guidance. Do not use for safety-critical, medical, legal, or financial decisions. Use at your own discretion; no warranties are provided; results depend on correct implementation and inputs.