7.13 — Packaging and IP handoff
• Deliverables. RTL for SSM-ALU and SSACC, C header with ISA opcodes and MMIO map, conformance vectors, CI testbench.
• Docs. One-page spec digest, band design guide, bring-up checklist.
• Licensing. Lane-only arithmetic IP; value-lane policies remain system-specific.
7.14 — Migration to full tiles and inference blocks (roadmap)
• A-MAC concept. Carry alignment through multiplies and {U,W} accumulations in neural inference; publish bands per tensor.
• Tile fusion. Co-locate SSM-ALU/SSACC with DSP slices for low-latency fusion in control/observability subsystems.
• Software parity. Maintain identical results in CPU/Python reference for every RTL change; CI blocks merges if conformance drifts.
7.15 — Power budgeting worksheet (quick method)
• Dynamic estimate. P_dyn := C_switch * V^2 * f_clk * alpha.
• Lane overhead. Measure P_on - P_off by clock-gating A/U-BUS and SSM blocks while running identical M-BUS traffic.
• Acceptance. Require delta_P / site_savings << 1 where site_savings comes from §6 levers; document at the build level.
7.16 — Formal properties (prove once, reuse)
• Finite map. |a| < 1 ⇒ atanh(a) finite.
• Inverse bound. tanh(atanh(a)) = a and |a| < 1 invariant after re-clamp.
• M2 closed forms. atanh( (a1+a2)/(1+a1*a2) ) = atanh(a1) + atanh(a2).
• Streaming linearity. U := sum_i w_i*atanh(a_i), W := sum_i w_i ⇒ order-invariant a_out := tanh(U/max(W, eps_w)).
Encode as SVA/SMT lemmas and attach proofs to the manifest.
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SSMH – Table of Contents
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